Overview
The core step of a Lindblad master-equation simulation is applying a precomputed propagator matrix P to a vectorized density matrix rho, over and over. lindblad-bench studies that operation in software and finds it memory-bound rather than compute-bound. This project realizes the same operation in hardware on a Sipeed Tang Nano 20K (Gowin GW2AR-18C).
The reason to move it to fabric is not throughput. It is determinism. Real-time quantum feedback control cares more about jitter than about peak FLOPs, and a cycle-exact pipeline gives a fixed answer to "when does the result arrive."
Architecture
A 4-stage pipeline runs the 9x9 complex product at 94 cycles per step amortized, with a 95-cycle single-step latency from the one-cycle fill.
| Stage | Operation | Hardware |
|---|---|---|
| S0 | Address generation, latch rho[col] | BSRAM address |
| S1 | Delay rho one cycle to match BSRAM read latency | Register |
| S2 | Four parallel 16x16 multiplies (ac, bd, ad, bc) | 4x DSP18 |
| S3 | Accumulate to 42 bits, saturate, store on col==8 | Adder + register |
Arithmetic is Q1.15 fixed point. Row sums that exceed the format saturate at full scale rather than wrapping.
Resource usage is 4 of 48 DSP18 blocks, roughly 880 of 20736 LUTs, and 2 of 46 BSRAM blocks for the real and imaginary halves of P.
The timing result
The board runs at 108 MHz, from a 27 MHz input through a 4x rPLL. That number is stress-characterized, not STA-derived.
nextpnr and apicula expose no timing arcs for the MULT18X18 primitive, so the DSP path is invisible to static timing analysis. The tool reports a clean result at frequencies where the hardware produces wrong answers. 135 MHz corrupts results under full-scale operands. 108 MHz passes 500 adversarial rounds.
This is the part worth keeping: when the timing model does not cover the path you care about, the operating point has to be established empirically, and the test that establishes it has to be adversarial rather than typical.
Error budget
Against double precision on a d=3 transmon trajectory:
| Source | Value |
|---|---|
| P quantization | 5.7e-05 HS, one-time |
| Floor truncation | bounded (-1, 0] LSB per component per step |
| Measured drift | ~1 LSB/step of trace, 3.05e-05/step, 6.1% over 2000 steps |
The fixed-point model in analysis/precision_test.py matches the RTL bit-exact, board-verified, so the budget is a property of the deployed design rather than of a simulation of it.
Toolchain
yosys, nextpnr, gowin_pack, openFPGALoader. No vendor tools anywhere in the flow. Verification is a golden-model self-checking testbench under Verilator.